Dram cell size is always of present concern as pressures continue to develop denser memories. Present design dictates that word lines and bitlines run perpendicular one another and that memory cells are arranged in pairs of two therewith sharing one bitline stud used to contact of the both memory cells with a bitline. FIG. 1 illustrates a top view and partial schematic of a conventional trench DRAM memory cell layout and FIG. 2 illustrates a 3-dimensional, partial cross-sectional drawing of a layout according to FIG. 1. Each pair memory cells is associated with two trench capacitors 1 and two active access consisting of drain (source) and buried strap 2 and gate 3 is associated with one BL stud and one drain (source) region 4 below. As first level of metal lines wordlines 5 are running over the active accsess decives forming the gates of the devices therewith. The bitline studs are connected to respective bit lines 6, BL.sub.n, where n is integer running on a second metal level perpendicular to the wordlines. The dimensions of a memory cell are commonly defined by the smallest feature size defined in fabricating the memory cell. Typically, the smallest feature size is equal to the width of the memory cell gate. Conventional DRAM memory cells measure 8 f.sup.2 per cell. Drawn to scale, this is demonstrated in FIG. 1, wherein 4 cells are enclosed within a 8 f by 4 f area. Thus (32 f.sup.2 /4 cell)=8 f/cell. For instance, a DRAM with a 0.15 micron minimum feature size includes a 0.3 .mu.m.multidot.0.6 .mu.m=0.18 (.mu.m).sup.2 chip area per cell. This gives a rectangular orientation with 2 cells laid out in one direction for every one cell in a perpendicular arrangement. A new layout is desired which will allow a more compact arrangement such as that which would exist with a square orientation.